Programmable logic devices (PLDs) exist as a well-known type of integrated circuit (IC) that may be programmed by a user to perform specified logic functions. There are different types of programmable logic devices, such as programmable logic arrays (PLAs) and complex programmable logic devices (CPLDs). One type of programmable logic device, known as a field programmable gate array (FPGA), is very popular because of a superior combination of capacity, flexibility, time-to-market, and cost.
An FPGA typically includes an array of configurable logic blocks (CLBs) surrounded by a ring of programmable input/output blocks (IOBs). The CLBs and IOBs are interconnected by a programmable interconnect structure. The CLBs, IOBs, and interconnect structure are typically programmed by loading a stream of configuration data (known as a bitstream) into internal configuration memory cells that define how the CLBs, IOBs, and interconnect structure are configured. An FPGA may also include various dedicated logic circuits, such as memories, microprocessors, digital clock managers (DCMs), and input/output (I/O) transceivers.
To implement a circuit design using an FPGA, the design is synthesized to produce a logical representation, which is then mapped onto programmable logic blocks, placed within the FPGA, and routed using the programmable fabric. The place and route phases of implementing a circuit design involve generating a layout of the circuit elements on the FPGA and defining the signal lines (routing resources) that connect the elements. When designing a circuit for an FPGA, a designer may utilize pre-defined circuit designs provided by a third party vendor on a fee basis. Such pre-defined circuit designs are referred to as intellectual property (IP) cores or IP blocks.
Vendors typically provide IP cores to their customers for a pre-defined evaluation period, after which the IP cores must be purchased. It is desirable to prevent unauthorized use of an IP core after the evaluation period has expired. Otherwise, the recipient of the evaluation IP core will be able to circumvent paying the fee for the core after the evaluation period has expired. Accordingly, there exits a need in the art for a method and apparatus for providing a protection circuit for protecting an integrated circuit design